1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming semiconductor devices that have capacitor and via contacts.
2. Description of the Related Art
In recent years, as the integration density of semiconductor devices increases, the area occupied by individual devices continues to decrease. Specifically, a capacitor for storing data of a dynamic random access memory (DRAM) is required to have sufficient capacitance irrespective of the decrease in the area occupied by the capacitor. Accordingly, a metal-insulator-metal (MIM) capacitor, in which a lower electrode and an upper electrode are formed of metal and separated by a layer of insulating material, have been used in many integrated circuit products. Additionally, MIM capacitors have been used extensively in semiconductor devices that perform analog-to-digital conversions and digital-to-analog conversions. Conversion between analog signals and digital signals requires that capacitors employed in such conversion processes be stable, i.e., the capacitance of the capacitor must be relatively stable over a range of applied voltages and temperatures. The capacitance of capacitors with polysilicon electrodes tends to be relatively unstable as the capacitance of such capacitor structures tends to vary with changes in temperature and applied voltage. Accordingly, capacitors with polysilicon electrodes are typically not used for such conversion applications.
In forming the upper and lower metal electrodes of a MIM capacitor an etching process is typically performed to pattern a metal layer. However, as the integration density of semiconductor devices has increased over the recent years, it has become more difficult to etch such metal layers. In particular, copper, which has good electro-migration resistance and a desirable low resistivity, is very difficult to etch. Accordingly, various methods for forming the upper and lower metal electrodes through a damascene process, a process which does not involve etching a metal layer, has been proposed. See, for example, U.S. Pat. No. 6,649,464. A copper damascene process generally comprises forming a trench for a copper structure in an insulation layer, forming a sufficient amount of copper to overfill the trench, and removing the excess copper from the substrate, thereby leaving the copper structure in the trench. However, the damascene process used in forming copper based capacitors and conductive lines and vias is a very time-consuming, expensive, multiple step process where chances for creating undesirable defects always exists.
The present disclosure is directed to various methods and of forming semiconductor devices that have MIM capacitors and via contacts.